1. Field of the Invention
The present invention is generally directed to semiconductor devices and to methods of fabricating the same. More specifically, the present invention is directed to vertical double diffused metal oxide semiconductor (VDMOS) devices and to methods of fabricating the same.
2. Background of the Invention
In integrated circuit (IC) products, such as hard disk drives (HDD), video tape recorders (VTR), and so forth, double-diffused metal oxide semiconductor (DMOS) devices are widely used in power conversion and control systems requiring high-power transfer and high-speed switching.
Advantageously, DMOS devices exhibit a high-speed switching characteristic, even when operating at a low gate voltage, while having a relatively low on-resistance and a high breakdown voltage. The low-voltage input terminal of the DMOS device results in minimal power consumption.
FIG. 1A is a cross-sectional view of a conventional DMOS device, and FIG. 1B is a top plan view thereof. Particularly, FIG. 1A is cross-sectional view taken along a line I-I′ of FIG. 1B.
Referring to FIG. 1A and FIG. 1B, an N-type buried layer 4 is formed at a semiconductor substrate 2. A drift region 6, which is lightly doped with N-type impurities, is epitaxially formed on the buried layer 4 and the substrate 2.
A plurality of P-type body areas 26 are formed at predefined areas of the drift region 6. A loop-shaped source area 30, which is heavily doped with N-type impurities, and a P-type bulk area 36, which is surrounded by the source area 30, are formed in each body area 26.
A sink area 8 is spaced from the outermost body areas 26, and is electrically connected to the buried layer 4 through the drift region 6. Between the sink area 8 and the outermost body area 26, a field oxide layer 16 is formed in contact with the sink area 8.
A drain area 32, which is heavily doped with N-type impurities, is formed on the sink area 8. The drain area 32 is loop-shaped and has a predetermined width, as shown in FIG. 1B. In the drain area 32, drain contacts 40 are formed at a constant spacing. The drain area 32 is connected to a drain electrode (not shown) through the drain contacts 40.
A gate electrode 20 is formed over a gate insulating layer 18 and the drift region 6, and is interposed between and partially overlaps the body areas 26. The gate electrode 20 is made of polysilicon. Also, an outer edge of the gate electrode partially overlaps the field oxide layer 16. The gate electrode 20 has a mesh-shaped structure in which a plurality of openings 22 are formed, as shown in FIG. 1B. A source contact 38 is formed in the respective openings 22 of the gate electrode 20. The source area 30 and the bulk area 36 are connected to a source electrode (not shown) through the source contact 38.
Returning to FIG. 1A, when a predetermined voltage is applied to a drain electrode and a gate electrode, electrons migrate from the source area 30 to a drain area 32 through a channel area 45, an accumulation region 47, the drift region 6, the buried layer 4, and the sink area 8.
Important electrical characteristics of the VDMOS device are an ON-resistance and a breakdown voltage. Here, the “ON-resistance” is the source-to-drain resistance when a transistor of the device is turned on.
The breakdown voltage is affected by the doping densities of the body area 26 and the drift region 6, and is structurally affected by the outermost body area 26 and the field oxide layer 16.
Reference is made to FIG. 1C for an explanation as to why the outermost body area 26 significantly affects the breakdown voltage. When the device operates at a high voltage, a depletion region 55 is formed at a P-N junction between the body area 26 and the drift region 6. The depletion region 55 is somewhat planar between the body areas 26, while having a curvature portion 60 outside the outermost body area 26. When a high voltage is applied to the DMOS device, an electric field concentrates on the curvature portion 60. Thus, the outermost body area 26 is vulnerable to a breakdown voltage. In FIG. 1C, the reference numeral and symbols ‘42’, ‘D’, ‘S’, and ‘G’ represent an interlayer insulating film, a drain electrode 56, a source electrode 57, and a gate electrode 20, respectively.
An effective way to improve the ON-resistance is to increase a doping density of the drift region 6 to thereby reduce a resistance at the drift region 6. Unfortunately, this lowers the breakdown voltage. In the meantime, if the doping density of the drift region 6 is lowered to thereby increase the breakdown voltage, the ON-resistance is increased.
In other words, when setting of the doping density of the drift region 6, there is a trade-off between increasing the doping density to obtain a low ON-resistance and decreasing the doping density to obtain a high breakdown voltage.